Pushkar Ranade, Intel’s chief technology officer Credit: Intel Corporation Intel could not make 10 times more leading-edge wafers even if it wanted to, says its chief technology officer, Pushkar Ranade. The world lacks the chipmaking tools. Doubling output is about the limit, he told Dwarkesh Patel on the Dwarkesh Podcast. Patel filmed the episode during a two-day tour of Intel’s most advanced fab in Oregon.
Patel asked whether the world had enough tools for Intel to make 10 times as many leading-edge wafers. “Not 10X, but probably 2X, yes,” Ranade said. Patel noted that AI compute has grown about threefold a year for a decade. Ranade said output could only rise faster if every supplier did too. “Unless everybody produces more, you can’t increase the output,” he said, naming equipment suppliers, their suppliers and their sub-suppliers. Tools are the bottleneck ASML makes fewer than 100 EUV lithography machines a year, Patel said.
Intel, TSMC and the memory makers all compete for them. Ranade said EUV is the biggest bottleneck but not the only one, as most chipmaking equipment is in short supply. Once a process like 18A is set, Intel needs the exact tools it was designed for. Intel can reuse about 80% of the 18A tools for the next node, 14A, he said.
Tools ordered today take about 18 months to arrive, Ranade said, which takes buyers into 2028. Building a new fab on top of that means the end of the decade. He added that Intel would have spent more on equipment had it known a year ago what it knows now. “Knowing what we know now, I think we’ll be investing more,” Ranade said. “We’re already there” On TSMC, Ranade drew a line between scale and technology. TSMC ships far more wafers, and catching up on that will be gradual, he said. “If you meant catching up in terms of just the technology, I think we’re already there,” Ranade said.
Patel cited SemiAnalysis figures suggesting Intel’s 14A, due in 2028, would match TSMC’s N2 on transistor density. “I would dispute your benchmarking,” Ranade replied, adding that density is only one measure. Chris Auth leads Intel’s process development. He said Intel offers ASML’s High-NA EUV machines on 14A because its chips move power lines to the back of the wafer. TSMC has said the machines do not make economic sense for it yet.
Auth put that down to TSMC lacking backside power. TSMC has announced its own version, called Super Power Rail, for its A16 node. Auth also said 18A “started out not having a PDK”. That is the design kit outside customers need to build chips at a foundry.
He said 14A will have one from the start. Memory, Musk and clean rooms Ranade was frank about Intel’s exit from memory. Intel sold its flash business to SK Hynix a few years ago. “Clearly, in hindsight, probably not the smartest time to sell off a flash memory business,” Ranade said. He added that the supply crunch is worse for memory than for compute today.
Intel is also working with Elon Musk on Terafab, the chip plant Tesla and SpaceX plan in Texas. Intel’s chief executive told Bloomberg this month that Intel will stay on the project. TSMC has said it is open to working on Terafab if it runs the fab. Ranade said building a fab is far more intricate than building a car, so Intel offered to work with Musk to speed his up.
He also questioned some of the industry’s oldest habits, including the clean room. “Do you really need a clean room today?” he asked. No incumbent would risk testing that on a live line, he said. A new fab can start from a clean slate. Ranade thanked Patel on X after the episode aired. @dwarkesh_sp It was fun to work with you and host you at our Oregon campus!
Love how you put all the many hours of wide-ranging conversations together in a succinct and coherent way! Pushkar Ranade (@magicsilicon) October 22, 2026 Also tagged with Get the TNW newsletter ✕ Close Get the TNW newsletter Get the most important tech news in your inbox each week.
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